In order to suppress the wiring delay caused by the scaling down of the semiconductor device, the attempts to reduce the wiring resistance and the wiring capacitance have been made. With respect to the wiring resistance, the measures by means of design technique and the adoption of the wiring made of copper to be a main conductor layer have been examined. For the formation of the copper wiring, the so-called damascene process is employed, in which metal for the wiring such as copper to be the main conductor layer is deposited on a substrate and on the surface of the trenches formed in an insulating film and then the superfluous metal outside the trenches is removed by the CMP (Chemical Mechanical Polishing) method, thus forming the wiring patterns in the trenches.
Meanwhile, with respect to the wiring capacitance, the adoption of the low dielectric constant material with the relatively low relative dielectric constant of about 2 to 3 has been examined. Above all, the film made of silicon-oxycarbite (referred to as SiOC, hereinafter) which is excellent in mechanical strength is considered as a promising low dielectric constant material.
Note that Japanese Patent Laid-Open No. 2001-326279 (Patent Document 1) discloses the technique, in which the insulating film that comes into contact with the copper wiring of the multilayered insulating film constituting the interlayer insulating film is formed by plasmanizing the film forming gas containing the alkyl compound having the siloxane bond and any one oxygen-containing gas of NH2O, H2O, and CO2, whose flow rate is equal to or less than the flow rate of the alkyl compound, and then reacting them mutually.
Also, Japanese Patent Laid-Open No. 2001-110789 (Patent Document 2) discloses the method of depositing and etching the intermetallic dielectric layer comprised of the first dielectric layer containing silicon, oxygen, and about 5% of carbon by atomic weight and the second dielectric layer containing silicon, oxygen, and about two-thirds or less of the carbon contained in the first dielectric layer.
Also, Japanese Patent Laid-Open No. 2002-203899 (Patent Document 3) discloses the technique for improving the adhesion between the interlayer insulating film and the barrier film by forming the interlayer insulating film with an SiO film, an SiOF film or an SiOC film and by forming the copper barrier film with an SiC film.
Also, Japanese Patent Laid-Open No. 2002-134494 (Patent Document 4) discloses the technique for preventing the crosstalk by forming the interlayer insulating film with an SiOC film, an SiOF film, or a CF film and forming the polishing stopper film for the CMP (Chemical Mechanical Polishing) and the copper barrier film with an SiC film.
Also, Japanese Patent Laid-Open No. 2002-353310 (Patent Document 5) discloses the technique for improving the etching of the vias by forming the interlayer insulating film with an SiOC film and forming the copper barrier film with an SiC film or an SiN film.
Also, Japanese Patent Laid-Open No. 2003-142593 (Patent Document 6) discloses the technique for forming an MIM (Metal Insulator Metal) capacitor by forming the interlayer insulating film with an SiO film, an SiOF film, or an SiOC film and forming the copper barrier film with an SiC film or an SiN film.
Also, Japanese Patent Laid-Open No. 2003-152076 (Patent Document 7) discloses the technique for improving the dielectric breakdown resistance of the wiring by forming the interlayer insulating film with an SiOC film, an SiOF film, a BF film, or a CF film, forming the polishing stopper film for the CMP with an SiC film, an SiN film, an SiO film, or an SiON film, and forming the copper barrier film with an SiOC film or an SiON film.
Also, Japanese Patent Laid-Open No. 2000-200832 (Patent Document 8) discloses the technique for improving the adhesion of the copper barrier film by forming the interlayer insulating film with an SiO film, an SiOF film, or an SiN film and forming the copper barrier film with an SiC film or an SiN film.
Also, Japanese Patent Laid-Open No. 2002-9150 (Patent Document 9) discloses the technique for preventing the aggregation of copper wiring by forming the copper diffusion preventing film of the copper damascene wiring to have a laminated structure of the first insulating film comprised of an SiN film, an SiC film, or an SiCN film and the second insulating film comprised of an SiN film.
Also, Japanese Patent Laid-Open No. 2002-373936 (Patent Document 10) discloses the technique in which an SiC film, an SiN film, an SiCN film, or an SiON film is used as the etching stopper film when forming the copper damascene wiring.
Also, Japanese Patent Laid-Open No. 2002-170882 (Patent Document 11) and Japanese Patent Laid-Open No. 2002-270691 (Patent Document 12) disclose the technique in which, in the process for forming the copper damascene wiring, after performing the CMP for filling copper into the trenches in the insulating film, the surface treatment of exposing the copper surface to the plasma of ammonia (NH3) or helium (He) is performed, and then, a copper diffusion preventing film such as an SiC film, an SiN film, or an SiCN film is formed.